In a typical data communications system data is sent from a transmitter to a receiver over a communications media such as a wire or fiber optic cable. In general, the data is encoded in a manner that facilitates effective transmission over the media. For example, data may be encoded as a stream of binary data (e.g., symbols) that are transmitted through the media as a serial signal.
In general, serial communication systems only transmit data over the communication media. That is, the transmitters in communications systems may not transmit a separate clock signal with the data. Such a clock signal could be used by a receiver to efficiently recover data from the serial signal the receiver receives from the communication media.
When a clock signal is not transmitted, a receiver for a serial communication system may include a clock and data recovery circuit that generates a clock signal that is synchronized with the incoming data stream. For example, the clock and data recovery circuit may process the incoming data stream to generate a clock signal at a frequency that matches the frequency of the data stream. The clock is then used to sample or recover the individual data bits (e.g., “symbols”) from the incoming data stream.
In a typical high speed application, symbols in a data stream are distorted as they pass through the media. For example, bandwidth limitations inherent in the media tend to spread the transmitted pulses. As a specific example, in optical communication systems chromatic dispersion and polarization mode dispersion which result from variation of light propagation speed as a function of wavelength and propagation axes may cause symbol spread.
If the width of the spread pulse exceeds a symbol duration, overlap with neighboring pulses may occur, degrading the performance of the receiver. This phenomenon is called inter-symbol interference (“ISI”). In general, as the data rate or the distance between the transmitter and receiver increases, the bandwidth limitations of the media tend to cause more inter-symbol interference.
To compensate for such problems in received signals, conventional high speed receivers may include filters and/or equalizers that, for example, cancel some of the effects of inter-symbol interference or other distortion. Examples of such components include a decision feedback equalizer (“DFE”) and a finite impulse response filter (“FIR”).
Moreover, some applications use adaptive filters or equalizers that automatically adjust their characteristics in response to changes in the characteristics of the communications media. Typically, the adaptation process involves generating coefficients that control the characteristics of the filter or equalizer. To this end, a variety of algorithms have been developed for generating these coefficients.
The least mean square (“LMS”) algorithm is commonly used for optimizing coefficients for various applications such as a finite impulse response filter and an adaptive equalizer such as a decision feedback equalizer. In general, an LMS algorithm generates adaptive coefficients by modifying the current coefficients based on an algorithm that takes into account current and prior samples of the received data. For example, for a two tap DFE the LMS algorithm may be described by the following equations:g1(n)=g1(n−1)+μ*e*y1  EQUATION 1g2(n)=g2(n−1)+μ*e*y2  EQUATION 2
where g(n−1) represents the coefficient immediately preceding coefficient (n), μ is a scalar that relates to, for example, the gain of a feedback loop and the speed with which the loop converges, e is an error signal, and y1 and y2 are prior samples of the received data.
Conventional receiver architectures may not provide optimum equalization of a received signal in high speed applications. For example, the LMS algorithm is not suitable for applications where prior samples of the received data are not available. However, it may be desirable to adjust components of a high speed receiver that do not retain prior samples of the data.
In addition, high speed receiver components may consume relatively large amounts of power and dissipate relatively large amounts of heat. For example, a typical high speed receiver that performs equalization in the digital domain incorporates a very fast digital to analog converter that has a relatively large resolution. Such a digital to analog converter may consume a large amount of power. Moreover, in very high speed CMOS applications (10 Gbps, for example), the high speed components may be implemented using shunt peaking techniques and on-chip spiral inductors. As a result, these components may occupy a relatively large area on the silicon chip. In addition, the use of these components may result in a design with longer interconnect lines and corresponding larger parasitic capacitance.
These and other characteristics of conventional architectures may have a negative impact on the performance of the receiver. Accordingly, a need exists for an improved receiver architecture, in particular for high speed applications.